Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!apple!baum
From: baum@Apple.COM (Allen J. Baum)
Newsgroups: comp.arch
Subject: R4000 - compatibilty questions
Message-ID: <49041@apple.Apple.COM>
Date: 11 Feb 91 22:12:33 GMT
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 35

[]
>In article <45792@mips.mips.COM> cprice@mips.COM (Charlie Price) writes:
>Superscalar is pretty easy to define, but
>what *does* superpipelining really mean?

 (details of R4000 pipe... Thanks!)
>
>Two instructions are issued per EXTERNAL clock,
>this is the same period as the on-chip cache latency.
>To do this, an internal clock runs at double the external clock and
>one instruction is issued per internal clock so
>This requires that cache access is pipelined.

This actually runs contrary to MY definition of superpipelined, which
is probably like MY definition of RISC - there's no such animal as THE
definition (for the curious, my definition requires all functional
units be multiple cycle- the R4000 behaves like a normal pipeline with
a multiple delay slot cache access [that's pipelined]).

I would expect a multiple cycle hit for taken branches as well, without
some kind of branch acceleration technique like a branch target cache.

I'm also curious about the compatibility provisions. Is there a
'mode'?  Are instructions 64 bits long now, or a mixture? Were just a few
new instructions added (like load/store double, shift double) and the
semantics of existing ones change (load becomes load signed/unsigned,
shifts become shift single, etc)? If there is a mode, does it just change
where in the word a condition is taken from? What else?

Inquiring minds would, of course, like to know. Is this level of detail
still subject to non-disclosure?

--
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