Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!uakari.primate.wisc.edu!dali.cs.montana.edu!ogicse!intelhf!ichips!ichips!glew From: glew@pdx007.intel.com (Andy Glew) Newsgroups: comp.arch Subject: Re: A Fast Memory Architecture Message-ID: Date: 12 Feb 91 02:06:03 GMT References: <2012@cluster.cs.su.oz.au> Sender: news@omews63.intel.com (News Account) Organization: Intel Corp., Hillsboro, Oregon Lines: 19 In-Reply-To: mrj@cluster.cs.su.oz.au's message of 9 Feb 91 03:53:36 GMT >Memory reference profiles for most applications show a moderately >sized set of very active clumps with little access elsewhere. >One possible DRAM configuration to match this would be to use >page mode DRAMS and spreading adjacent pages systematically >or randomly across the different chips. Each chip has a >different currently active page allowing quick access to almost >as many pages as there are chips - assuming you have randomised >the pages across the chips properly. All you would need to >implement this would be a more complex, MMU like, DRAM controller. Wouldn't be nice if you could have several such "active sets" per chip? I've known at least one microprocessor architect to scream about this. -- Andy Glew, glew@ichips.intel.com Intel Corp., M/S JF1-19, 5200 NE Elam Young Parkway, Hillsboro, Oregon 97124-6497