Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!olivea!uunet!mcsun!ukc!cam-eng!dscy
From: dscy@eng.cam.ac.uk (D.S.C.Yap)
Newsgroups: comp.arch
Subject: Re: R4000 "announcement" (64-bit stuff)
Message-ID: <22599@rasp.eng.cam.ac.uk>
Date: 12 Feb 91 13:46:26 GMT
References: <90@shasta.Stanford.EDU> <1991Feb8.055009.9883@ico.isc.com> <45789@mips.mips.COM>
Sender: dscy@eng.cam.ac.uk
Lines: 22

In article <45789@mips.mips.COM>, mash@mips.COM (John Mashey) writes:
> 
> AND, OF COURSE:
> 6) Technical number-crunchers: have NEVER fit in ANY space :-)
> 

Right, and they're never fast enough either :-(  Someone said that the
ANTICIPATED performance of systems based on this chip started around 50
mips.  That's nice, but I'd like someone to take a stab at an ANTICIPATED
mflop rating which interests me infinitely more.  Any takers?

Davin

PS:  Don't flame me for asking, I just like numbers - meaningless or otherwise.

          .oO tuohtiw esoht fo noitanigami eht ot gnihton evael Oo.
      Davin Yap, University Engineering Department, Cambridge, England
                       -->  dscy@eng.cam.ac.uk  <--
--
          .oO tuohtiw esoht fo noitanigami eht ot gnihton evael Oo.
      Davin Yap, University Engineering Department, Cambridge, England
                       -->  dscy@eng.cam.ac.uk  <--