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From: davidb@brac.inmos.co.uk (David Boreham)
Newsgroups: comp.arch
Subject: Re: A Fast Memory Architecture
Message-ID: <14356@ganymede.inmos.co.uk>
Date: 12 Feb 91 14:37:31 GMT
References: <2012@cluster.cs.su.oz.au> <1991Feb10.013525.1317@zoo.toronto.edu>
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Reply-To: davidb@inmos.co.uk (David Boreham)
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In article <1991Feb10.013525.1317@zoo.toronto.edu> henry@zoo.toronto.edu (Henry Spencer) writes:
>A major problem with this is that DRAMs typically are only one bit wide.
>So the minimum unit of memory is a 32-chip bank, not a single chip.
>You can buy wider DRAMs, but in general they need extra pins, and this
>means a bigger package that eats more board space; there is *very* strong
>economic and practical pressure toward 1-bit-wide DRAMs, and this will
>continue as long as a substantial number of DRAMs are needed to meet
>a system's memory requirements.  (Of late, the software people's memory
>needs have shown a regrettable ability to match or exceed the growth in
>chip capacity.)

I don't disagree strongly with anything Henry says but I think his
direction is a bit out of date. The number of chips, and certainly
the board area required, for a computer's memory has decreased over
the past ten years--steadily. The 4Mb on our ten-year-old VAX using
64K chips takes 512 chips. The 64Mb on the machines we use now takes
128 chips and those chips use about a quarter the board area of the
64K DIPs. The memory is only three times as fast though and this is
probably the real problem :)

There is a definite trand towards wider RAMs. At 64K you
could only get 'by 1' chips. At 256K you could get by 1
and by4. At 1M you can now get by1, by4, by8 and by16.
You can also get modules at up to by36.

If you have a processor which supports multiple memory
banks and RAS precharge interleaving then four banks
of 32-bit wide, done with by8 chips might well be faster
than one bank of 64-bit wide memory done with by4 chips.

Note that it is by no means obvious that running multiple
banks each with an ``open page'' held active (either using
page-mode or static column) will actually be a performance
win. A recent copy of Electronics carried an item which 
claimed that such a feature could speed up a memory system
by 300% ! In fact, since you need to provide RAS precharge
(which is about the same time as the memory access time)
when the page turns out to be wrong; and you can't tell
if it is wrong until you need the data, if the accesses
are hopping about then the precharge times will kill the
access time. 

Also you burn power in all the banks all the time.


David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb
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