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From: rtrauben@cortex.Eng.Sun.COM (Richard Trauben)
Newsgroups: comp.arch
Subject: 64bits: Area Overhead and Opportunity Costs
Summary: 64bit addresses or 2x cache capacity... NOT both.
Message-ID: <7967@exodus.Eng.Sun.COM>
Date: 14 Feb 91 05:10:25 GMT
Sender: news@exodus.Eng.Sun.COM
Lines: 55

In article <1991Feb12.225634.13757@m.cs.uiuc.edu> (Don Gillies) writes:
>I read an article today in "The Microprocessor Report" that said the
>increase from 32 to 64 bits added approximately 10-15% to the size of
>the chip.  This is quite surprising.  You'd think that going from 32
>to 64 bits would double the size of the ALU and all the data paths and
>registers.  Does this mean that the datapath and ALU and all the
>registers accounted for only 10-15% of the microprocessor to begin
>with?  What is the baseline design for this 10-15% increase in area?

At first blush, the projected 15% area overhead for increasing the datapath 
width from 32bits to 64bits DOES sound very low. However, consider the 
following 'typical' area budget characteristics for a highly integrated 
single chip processor:

Let 1/3 of the area budget be on-chip cache, 1/3 floating point unit and
1/3 be integer unit. A move to 64bits will have virtually no impact on
the fp engine. While the area for tags double, large data block caches 
(i.e. 32-64bytes/tag) make this increase in tag ram area neglectable.

Finally assume the integer unit is 1/2 datapath and 1/2 control. The
exact percentage will depend on your favorite processor architecture
and implementation.  A first order approximation of the area impact
is that the control section area stays constant while the datapath 
area doubles.

uP 		Fraction of Total	Effect 64-bit	
Sub-Block	32bit Area Budget	on 32bit Area
----------   	-----------------       -------------
FPU	 	.33			1.0x=>	.33
$	 	.33			1.1x=>	.36
IU	 	.33 ==>.5dpth->.16	2.0x=>	.32
	     	    ==>.5cntl->.16	1.0x=>	.16
	       -------------------	-----------
	       1.00A 			       1.17A 

This back of the envelope calculation says area would increase by 17%
by pasting a 64-bit IU core onto a generic design. Obviously the exact
mileage will vary somewhat. 

** OPINION **
It also suggests, for a fixed manufacturable die size with all other things 
being equal, that the quantitative cost to the customer for going to 64bit 
addressing in advance of truly needing it is analogous to not providing 1/2 
the capacity of on-chip cache that they might have had otherwise. A common
rule of thumb states that doubling the cache size will half the overall cache
miss penalty.

Simular arguments could be applied about the opportunity costs of
an integrated FP engine on the high integration processor. 

There are opportunity costs in each engineering tradeoff made. You only get 
what you pay for... sometimes less :-). 

Regards,
-Richard Trauben