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From: rogerk@MIPS.com (Roger B.A. Klorese)
Newsgroups: comp.arch
Subject: Re: On-Chip Cache Survey
Message-ID: <578@spim.mips.COM>
Date: 14 Feb 91 17:31:43 GMT
References: <16616@sdcc6.ucsd.edu> <574@spim.mips.COM>
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In article <574@spim.mips.COM> rogerk@mips.COM (Some Idiot) writes:
>In article <16616@sdcc6.ucsd.edu> jlodman@beowulf.ucsd.edu (Michael Lodman) writes:
>>The following is the list of micros with on-chip cache I've received
>>to date. Thanks to all who helped out!
>>Mips		R4000
>...and R6000.

Wrong.

While the R6000 has a two-level cache like the R4000, both levels are 
implemented off-chip.
-- 
ROGER B.A. KLORESE                                  MIPS Computer Systems, Inc.
MS 6-05    930 DeGuigne Dr.   Sunnyvale, CA  94088              +1 408 524-7421
rogerk@mips.COM         {ames,decwrl,pyramid}!mips!rogerk         "I'm the NLA"
"WAR: been there, done that... hated it."  -- QueerPeace/DAGGER chant