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From: lindsay@gandalf.cs.cmu.edu (Donald Lindsay)
Newsgroups: comp.arch
Subject: 4T cache cells?
Message-ID: <11959@pt.cs.cmu.edu>
Date: 15 Feb 91 04:55:10 GMT
Organization: Carnegie Mellon Robotics Institute, School of CS
Lines: 10


The Microprocessor Report says that the R4000's onchip cache uses
four-transistor memory cells, instead of the 6T cells used by Intel
and Motorola.

Is some new trick involved? Perhaps the higher clock rates make a
difference? Or is MIPS just willing to skate on thinner ice? (I
notice that the onchip caches are parity protected.)
-- 
Don		D.C.Lindsay .. temporarily at Carnegie Mellon Robotics