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From: gunther@probitas.cs.utas.edu.au (Bernard Gunther)
Newsgroups: comp.arch
Subject: Re: 4T cache cells?
Keywords: cache RAM cells
Message-ID: <1972@diemen.utas.edu.au>
Date: 15 Feb 91 12:13:20 GMT
References: <11959@pt.cs.cmu.edu>
Sender: news@diemen.utas.edu.au
Followup-To: gunther@probitas.cs.utas.edu.au (Bernard Gunther)
Organization: Dept. of Computer Science, University of Tasmania
Lines: 26

In article <11959@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes:
>
>The Microprocessor Report says that the R4000's onchip cache uses
>four-transistor memory cells, instead of the 6T cells used by Intel
>and Motorola.
>
>Is some new trick involved? Perhaps the higher clock rates make a
>difference? Or is MIPS just willing to skate on thinner ice? (I
>notice that the onchip caches are parity protected.)

I suspect that with the high density technology they're using, MIPS
are able to use high-resistance polysilicon resistors as transistor loads
instead of the larger PMOS loads commonly used.  Cache cells can then be
packed closer, since only four NMOS transistors are used per cell (2 for
storage, 2 for gating to bit lines) and a single, continuous p-well can
be used for their substrate.

This has been common practice in very high density SRAMs for a few years
now.  The downside is that the cells store less charge and have been
shown to have higher soft error rates than PMOS load RAMs.  Perhaps this
justifies the inclusion of on-chip parity...

--
Bernard K. Gunther        Internet: gunther@probitas.cs.utas.edu.au
Department of Computer Science, University of Tasmania
GPO Box 252C, Hobart, Tasmania 7001, AUSTRALIA   Tel: (002) 202951