Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!newstop!eastapps!pyrite!sgolson
From: sgolson@pyrite.East.Sun.COM (Steve Golson)
Newsgroups: comp.arch
Subject: Re: 4T cache cells?
Message-ID: <4323@eastapps.East.Sun.COM>
Date: 15 Feb 91 22:34:56 GMT
References: <11959@pt.cs.cmu.edu>
Sender: news@East.Sun.COM
Reply-To: sgolson@east.sun.com (Steve Golson)
Organization: Sun Microsystems, Billerica MA
Lines: 11

In article <11959@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes:
>The Microprocessor Report says that the R4000's onchip cache uses
>four-transistor memory cells, instead of the 6T cells used by Intel
>and Motorola.

Moto uses 4T cells for the 68020 and 68030. Honest-to-gosh 4T cells, with
no poly pullups. They require periodic refreshing.

Steve Golson -- Trilobyte Systems -- Carlisle MA -- sgolson@east.sun.com
       (consultant for, but not employed by, Sun Microsystems)
"As the people here grow colder, I turn to my computer..." -- Kate Bush