Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!usc!bbn.com
From: tdonahue@bbn.com (Tim Donahue)
Newsgroups: comp.realtime
Subject: Re: Real-Time Harris
Keywords: Real Real-Time Unix
Message-ID: <62657@bbn.BBN.COM>
Date: 11 Feb 91 16:18:23 GMT
References: <983@hrshcx.csd.harris.com>
Sender: news@bbn.com
Reply-To: tdonahue@bbn.com (Tim Donahue)
Organization: BBN Advanced Computers, Inc.
Lines: 44
In-reply-to: steved@hrshcx.csd.harris.com (Steve Daukas)

In article <983@hrshcx.csd.harris.com>, steved@hrshcx (Steve Daukas) writes:
>
><much deleted, see prior posting>
>
Thank you for taking the time to find out and reply, Steve.  This sort
of information may be hard to obtain.  To summarize, I'd say your system
has the following specifications:

0. Machine:  88100, 25 MHz, up to 128 Kb cache (? I / ? D)

1. OS:  Harris CX/RT

2. Time from interrupt signal active to first instruction of interrupt
	handler:  < 5 microseconds

3a. Time from interrupt signal active to first instruction of interrupt
	handler which does useful work (i.e., 88100 "thawed", interrupts
	reenabled, necessary context saved, etc.): 27 microseconds
	(Note that this is somewhat different from "interrupt response
	time < 5usec")

3b: Time from user interrupt handler return (executing "jmp r1") to
	interrupted instruction in task or lower-priority ISR: 
	? microseconds

4.  Time required to switch from one user task to another, same CPU:
	(about) 40 microseconds

5.  Time required for task on CPU 1 to ready task on CPU 2: ? microseconds

Note:  All measurements performed under favorable cacheing conditions.

Cheers,
Tim

Timothy P. Donahue
Operating Systems Development Group
BBN Advanced Computers, Inc.
10 Fawcett Street
Cambridge, MA 02138
(617) 873-6000

tdonahue@bbn.com
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