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From: henry@ginger.sri.com (Henry Pasternack)
Newsgroups: comp.sys.m68k
Subject: Question about Signetics 74F1763 DRAM controller.
Message-ID: <21198@unix.SRI.COM>
Date: 13 Feb 91 19:02:50 GMT
Sender: news@unix.SRI.COM
Reply-To: henry@ginger.sri.com (Henry Pasternack)
Organization: SRI International
Lines: 29


   Hi.  I'm designing a 68030-to-DRAM interface using 60 nS fast
page-mode memory.  I've been trying to choose an integrated memory
controller, but each chip I've looked at seems to have some fatal
flaw.  I thought the 74F1763 would do the trick, but then I found
what looks like a problem.  Maybe someone can help me resolve the
following question which concerns refresh arbitration during page-
mode accesses.

   I intend to support both cache burst and non-cache burst page
mode DRAM accesses.  The 74F1763 has a PAGE input which causes
RAS to be asserted continuously during page-mode accesses.  During
lengthy page-mode accesses, refresh requests are logged internally
(up to 128) and handled in a burst following the end of the access.

   Well, what happens if the CPU loops in page for more than 128
refresh requests?  The 74F1763 doesn't have an external refresh
request pin, so there's no way to find out a refresh request has
been missed.  There is a memory grant (GNT) signal which is used to
indicate the result of refresh/access arbitration.  It would be nice
if the 74F1763 would deassert GNT during a burst access upon the
overflow of the refresh logger, but I don't think it can do that.

   Does anyone have any additional information on this topic?  Enquiring 
minds need to know.

   Thanks.

-Henry