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From: cprice@mips.COM (Charlie Price)
Newsgroups: comp.sys.mips
Subject: Re: Load Delays -- a question
Message-ID: <45807@mips.mips.COM>
Date: 12 Feb 91 02:29:40 GMT
References: <45672@mips.mips.COM> <1991Feb9.221451.22230@athena.mit.edu> <45762@mips.mips.COM> <1991Feb11.043136.14845@athena.mit.edu>
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Reply-To: cprice@mips.COM (Charlie Price)
Organization: MIPS Computer Systems, Inc
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In article <1991Feb11.043136.14845@athena.mit.edu> jfc@athena.mit.edu (John F Carr) writes:
>In article <45762@mips.mips.COM> cprice@mips.COM (Charlie Price) writes:
>
>>The only way not to stall when the instruction or data that you 
>>want isn't available is if you are prepared to forge ahead and 
>>try to execute instructions out of order.
>
>I meant cache miss for data, not instruction fetch.

Clearly it would be faster not to stall on cache misses
-- if you can do that at the same speed.
I don't design these things, but the folks who do tell me
that this is VERY complicated.

>I brought this up because I do much of my programming on an IBM RT, which
>allows 2 outstanding load operations which normally need 5 cycles to
>complete. 

The RT doesn't have a cache, right?
That makes some difference in how you approach loads and stores --
and some difference in the performance of the system.
-- 
Charlie Price    cprice@mips.mips.com        (408) 720-1700
MIPS Computer Systems / 928 Arques Ave. / Sunnyvale, CA   94086-23650