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From: sllu@jenny.isi.edu (Shih-Lien Lu)
Newsgroups: sci.electronics
Subject: Analog signal elay element: Question
Message-ID: <16663@venera.isi.edu>
Date: 6 Feb 91 19:01:54 GMT
Sender: news@isi.edu
Reply-To: sllu@ISI.EDU (Shih-Lien Lu)
Organization: USC-Information Sciences Institute
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Wisdom of the net:

What are some ways to implement delays for analog signals (dealy in 1 ns
resolution)?
One possible way is to have the equiv. of an R/2R ladder.
Is there any other way, in particular, to implement on an IC?
Thanks in advance. 

Shih-Lien