Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!uunet!shelby!cascade.stanford.edu!dolores!raje From: raje@dolores.Stanford.EDU (Prasad Raje) Newsgroups: comp.arch Subject: Re: 64-bit addressing Message-ID: Date: 18 Feb 91 17:35:59 GMT References: <4270@lectroid.sw.stratus.com> <1991Feb18.032849.16544@uicbert.eecs.uic.edu> Sender: news@cascade.Stanford.EDU (USENET News System) Organization: Center for Integrated Systems, Stanford Lines: 32 In-Reply-To: wilson@uicbert.eecs.uic.edu's message of 18 Feb 91 03:28:49 GMT First the statement: A 64 bit address will be able to address each byte in a memory array 10.4 kilometers on each side, populated chock full with 1Gbit DRAMs. put differently You will require a square 10.5 kilometers on a side completely filled with 1Gbit DRAMs to exhaust the addressability of a 64 bit byte pointer. (the thought of 1Gbit DRAMs from Stanford to Sunnyvale is weirdly attractive) The (simple) math: 1 GBit DRAMS should be available by 2000 A.D. and are estimated to each occupy an area of 8 cm^2. 1 GByte (2^30) of memory occupies 64 cm^2. 2^64 bytes of memory will occupy 64 x 2^34 cm^2. Put the chips edge to edge (never mind interconnect, maybe we will have parallel optical connections in the Z direction) and you end up with a square 10.5 kilometers on a side (6.6 miles for you non metric types) So the question is, just what kind of store is a processor or even a massive bevy of processors going to address with 64 bit pointers? Maybe we are talking about addressing files on disk. I am not intimately familiar with disk storage densities - but my impression is that it is not much denser (surface area/bit) than DRAM bit density. (please correct me if I am wrong) Prasad (just getting a feel for how big 2^64 really is)