Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!clyde.concordia.ca!nstn.ns.ca!news.cs.indiana.edu!sdd.hp.com!usc!apple!baum
From: baum@Apple.COM (Allen J. Baum)
Newsgroups: comp.arch
Subject: Re: 4T cache cells?
Message-ID: <49311@apple.Apple.COM>
Date: 18 Feb 91 19:01:27 GMT
References: <11959@pt.cs.cmu.edu> <4323@eastapps.East.Sun.COM>
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 32

[]
>In article <4323@eastapps.East.Sun.COM> sgolson@east.sun.com (Steve Golson) writes:
>
>Moto uses 4T cells for the 68020 and 68030. Honest-to-gosh 4T cells, with
>no poly pullups. They require periodic refreshing.


I don't believe that this is the case. I asked Moto about 4T cells for caches
(and DRAM cells), and was told that the 680x0 had 6T cells, and the 88200,
which uses a different process, has 4T cells with poly loads.

There is one microprocessor I'm aware of which uses dynamic RAM internally,
and that's an ATT DSP. I looked into it a little (using DRAM, that is),
figuring if you could use one or 2 T's you could fit twice as much cache on
a chip. The answer seems to be that it would be too slow, and to make it
fast you have to make the transistors really big, wiping out the space savings,
or you'd have to play enough tricks with the decoding that the noise spikes
would wreak havoc on the stored charges and it would be unreliable.

There have been a couple of papers about DRAM caches. One suggested a valid
bit which was guaranteed to leak away faster than the data. So, if the
data was going ad, it would also be marked invalid & wouldn't be used. This
is a real LRU scheme, you'll notice!

Another paper was published in a Hawaiian conference, but I wasn't able to
go (rats) and haven't read the proceedings. Has anyone seen that paper, and
can you summarize? Any other pointers to papers on the subject?


--
		  baum@apple.com		(408)974-3385
{decwrl,hplabs}!amdahl!apple!baum