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From: david@neutron.amd.com (David Witt)
Newsgroups: comp.arch
Subject: Re: 4T cache cells?
Message-ID: <1991Feb19.134006.29251@mozart.amd.com>
Date: 19 Feb 91 13:40:06 GMT
References: <11959@pt.cs.cmu.edu> <4323@eastapps.East.Sun.COM> <49311@apple.Apple.COM>
Sender: usenet@mozart.amd.com (Usenet News)
Organization: Advanced Micro Devices, Austin, TX
Lines: 40

In article <49311@apple.Apple.COM> baum@apple.UUCP (Allen Baum) writes:
| []
| >In article <4323@eastapps.East.Sun.COM> sgolson@east.sun.com (Steve Golson) writes:
| >
| >Moto uses 4T cells for the 68020 and 68030. Honest-to-gosh 4T cells, with
| >no poly pullups. They require periodic refreshing.
| 
| 
| I don't believe that this is the case. I asked Moto about 4T cells for caches
| (and DRAM cells), and was told that the 680x0 had 6T cells, and the 88200,
| which uses a different process, has 4T cells with poly loads.

	I was at Motorola Microprocessor Design when the 68020 was originally
	designed, so this is what I was aware of at the time.

	I am sure the 68020 used 4T cells with dynamic refresh, the refresh
	occuring about once every 256 clocks or so.  This was one of
	the reasons for the 8mhz minimum clock frequency.  

	I believe they decided on the 68030 that this was more trouble
	than it was worth, especially considering the size of the arrays
	they were dealing with, and went to 6T Ram cells, which they
	stayed with when they finished the 68040.

	The 88200 used a poly-load SRAM process, and as such built it's RAM
	arrays with a 4T poly.  I am not sure what the plans are for their
	next generation, but I would probably guess they would go with
	6T Ram cells similar to the 68040.


	David Witt




--
	David Witt		1-(512)-462-5846
        Advanced Processor Development
	Advanced Micro Devices	domainLand:  david@neutron.AMD.COM
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