Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!hellgate.utah.edu!caen!zaphod.mps.ohio-state.edu!magnus.ircc.ohio-state.edu!tut.cis.ohio-state.edu!sei!ajpo!carters From: carters@ajpo.sei.cmu.edu (Scott Carter) Newsgroups: comp.arch Subject: Re: R4000 Summary: Trying to figure out R4000 latencies Message-ID: <756@ajpo.sei.cmu.edu> Date: 19 Feb 91 22:43:39 GMT Lines: 36 References: <45448@mips.mips.COM> <1991Feb1.223326.18683@watdragon.waterloo.edu> <45525@mips.mips.COM> <45792@mips.mips.COM> Reply-To: carter%csvax.decnet@mdcgwy.mdc.com Organization: McDonnell Douglas Electronic Systems Company In article <45792@mips.mips.COM> cprice@mips.COM (Charlie Price) writes: Looking at this pipeline, it looks as if a branch has three microcycle delay slots. Is this correct (assuming that branch condition is resolved at the end of RF) ? What about load delays? When does the load bypass to the source register? (assuming the stall case)? Is the load aligner in the tag check or DS phase (i.e. is the latency of partial or unaligned load the same as an integer load [although with a 64-bit datapath there's a 2-way mux and sign extend (??) even for an integer load]). Are there bypasses for the weirder cases (like bypass after TC if the primary bypass is at DS, load pipe to store pipe bypass, etc.)? How do stores work? I can think of lots of possibilities ... Is the pipelining of word stores and partial word stores the same? uPReport (p 9, 2nd paragraph) says the O-cache freezes during write of a dirty line. Given the line-wide write buffer, why the freeze? Minds with nothing better to do want to know :) >Charlie Price cprice@mips.mips.com (408) 720-1700 >MIPS Computer Systems / 928 Arques Ave. / Sunnyvale, CA 94086-23650 Scott Carter - McDonnell Douglas Electronic Systems Company carter%csvax.decnet@mdcgwy.mdc.com (preferred and faster) - or - carters@ajpo.sei.cmu.edu (714)-896-3097 The opinions expressed herein are solely those of the author, and are not necessarily those of McDonnell Douglas.