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From: connors@hplabsz.HP.COM (Tim Connors)
Newsgroups: comp.arch
Subject: Translating 64-bit addresses
Message-ID: <6590@hplabsz.HP.COM>
Date: 19 Feb 91 20:55:11 GMT
Reply-To: connors@hplabs.hp.com (Tim Connors)
Organization: Hewlett-Packard Laboratories
Lines: 25

Now that we've entered the brave new world of 64 bit (flat) address spaces,
is it time to revive the old flame wars on address translation mechanisms?

For 32 bit addresses, Motorola's MC68851 uses a "two level" translation
tree involving 4K pages (12 bits) and two 10 bit indices, one index for
each level.  How could this technique be applied to 64 bit addresses?
Would more levels be needed?  Should the page size be larger?

More interestingly, could the pointers which link one level to the next be
only 32 bits and thus save on translation table size?  This might
limit the placement of the tables in a machine with more than 4Gbytes of RAM.
It also requires switching from 64 to 32 bit mode during TLB miss handling.

What about inverted page tables.  Would they be any better for 64 bit
addresses?  Does this make life tough for the MACH operating system?

Are 64 bit addresses spaces more likely to be sparse?  What affect does that
have on the translation mechanism?

I can think of alot more questions, but I'll leave it there except to ask
if anyone from MIPS can tell us how you intend to do address translation on
the R4000?

Sincerely,
Tim