Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!usc!zaphod.mps.ohio-state.edu!magnus.ircc.ohio-state.edu!csn!arrayb!wicklund From: wicklund@intellistor.com (Tom Wicklund) Newsgroups: comp.arch Subject: Re: 64-bit addressing Message-ID: <1991Feb19.214750.6489@intellistor.com> Date: 19 Feb 91 21:47:50 GMT References: <4270@lectroid.sw.stratus.com> <1991Feb18.032849.16544@uicbert.eecs.uic.edu> Distribution: usa Organization: Intellistor Lines: 24 In raje@dolores.Stanford.EDU (Prasad Raje) writes: >First the statement: >A 64 bit address will be able to address each byte in a memory array >10.4 kilometers on each side, populated chock full with 1Gbit DRAMs. >You will require a square 10.5 kilometers on a side completely filled >with 1Gbit DRAMs to exhaust the addressability of a 64 bit byte pointer. >(the thought of 1Gbit DRAMs from Stanford to Sunnyvale is weirdly attractive) Before deciding how rediculous a fully populated 64 bit address space is, consider whether or not a full 64 bit space will appear immediately. The short term need is for >32 bit. I imagine that processors might be built with 36, 40, 48, etc. physical address lines rather than a full 64. How many real systems today implement more than 24-26 bits of physical address even though the chips can handle 32? Alternately, consider the size of a 4GB memory back in the early 80's when 32 bit addresses were being designed into processors. The dominant memory chip was 256K, so you'd need 131,000 chips to implement the memory. Obviously rediculous at the time.