Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!thunder.mcrcim.mcgill.edu!snorkelwacker.mit.edu!spool.mu.edu!uunet!world!iecc!compilers-sender From: Chuck_Lins.SIAC_QMAIL@gateway.qm.apple.com (Chuck Lins) Newsgroups: comp.compilers Subject: Machine Descriptions Keywords: GCC, design Message-ID: <9102201924.AA14610@internal.apple.com> Date: 20 Feb 91 16:20:39 GMT References: <2395@taurus.BITNET> Sender: compilers-sender@iecc.cambridge.ma.us Reply-To: Chuck Lins Organization: Compilers Central Lines: 21 Approved: compilers@iecc.cambridge.ma.us In a previous posting and subject, Michael Orr asks about retargeting GCC to an unusual machine type. I'd like to raise the question about machine descriptions in general. It seems from all the papers I've read on this topic that the research has focused on the VAX-11, MC680x0, PDP-11, IBM 360/370 kind of architecture. I don't remember much being done with SPARC, MIPS, HP-PA RISC, 88000, ARM, architectures. Everybody ignores floating-point (and fp coprocessors). And almost no one addresses run-time environments (I remember one paper but I forget the author). It seems that we're a very long way from a truely general machine description mechanism. So long as you remain in the 'normal' and 'standard' kinds of architectures machine description is ok; otherwise you have to build your back-end the "old-fashioned" way - by hand. (IMHO you can still take advantage of newer compiler technology, it's just not automated. You might even have to find your own peephole optimizations.) Is this an accurate assessment? If not, I'm sure someone will happily point out the gaps in my knowledge (which I know to be significant :-) -- Send compilers articles to compilers@iecc.cambridge.ma.us or {ima | spdcc | world}!iecc!compilers. Meta-mail to compilers-request.