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From: rajeev@acura.ece.cmu.edu (Rajeev Jayaraman)
Newsgroups: comp.lsi.cad
Subject: Large placement benchmarks needed
Keywords: Placement, Benchmarks
Message-ID: <1991Feb18.153708.21979@fs7.ece.cmu.edu>
Date: 18 Feb 91 15:37:08 GMT
Sender: news@fs7.ece.cmu.edu (USENET News System)
Reply-To: rajeev@acura.ece.cmu.edu (Rajeev Jayaraman)
Organization: Electrical and Computer Engineering, Carnegie Mellon
Lines: 27
Originator: rajeev@acura.ece.cmu.edu


I am working on a massively parallel layout
synthesis system and I would like 
to test this system on large industrial placement
benchmarks.  Specifically I 
am looking for:

1. Approximately 25000 or more placeable objects.
2. Some sort  of row-based placement  (standard 
cell, gate array, sea-of-gates)
3. Exact locations for pads on the periphery of
the placement area.

In order to preserve confidentiality, I don't need
a full functional description
of the circuit, I can work with network
descriptions that  just have simple gate
and net connections. I would appreciate hearing
from  people with such placement
benchmarks. 

Thanks in advance
Rajeev (rajeev@acura.ece.cmu.edu)

ps:  I  do know about the  MCNC benchmark suite,
and I   am looking beyond those
benchmarks.