Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!helps!bigtex!james
From: james@bigtex.cactus.org (James Van Artsdalen)
Newsgroups: comp.sys.ibm.pc.hardware
Subject: 16 bit memory cycles & MEMCS16 (was Re: Dual monitors)
Message-ID: <54860@bigtex.cactus.org>
Date: 20 Feb 91 01:18:43 GMT
References: <166@cf_su20.cf_su10.Sbi.COM> <26810@uflorida.cis.ufl.EDU> <8130@davidsys.com> <1991Feb12.010248.7563@cs.mcgill.ca> <8345@david
Reply-To: james@bigtex.cactus.org (James Van Artsdalen)
Organization: Institute of Applied Cosmology, Austin TX
Lines: 54

In <8345@davidsys.com>, douglass@davidsys.com wrote:

> In article <1991Feb12.010248.7563@cs.mcgill.ca>, phil@cs.mcgill.ca
	(Philip LOCONG) writes:

| As earlier posts suggested it, the ISA bus specifications force the bus
| to run each 128k section of RAM entirely in 8-bit mode or entirely in
| 16-bit mode, that means the A-B section has to be either 8 or 16-bit.

This is exactly correct.

> Excuse me, but you're *WRONG*.
> I've already run a test that indicates otherwise.

Design considerations are not done by running one test and declaring
victory.  There are things called "specifications".

From the IBM AT Technical Reference Manual description of MEMCS16
(page 1-27 in mine):

	'-MEM 16 Chip Select' signals the system board if the present
	data transfer is a 1 wait-state, 16-bit, memory cycle.  It
	must be derived from the decode of LA17 through LA23.

Description of the SA address lines (page 1-22):

	SA0 through SA19 are gated onto the system bus when 'BALE' is
	high and are latched on the falling edge of 'BALE'.

Description of the LA address lines (also page 1-22):

	These signals are valid when 'BALE' is high.  LA17 through
	LA23 are not latched during microprocessor cycles and
	therefore do not stay valid for the whole cycle.  Their
	purpose is to generate memory decodes for 1 wait-state memory
	cycles.  These decodes should be latched by I/O adapters on
	the falling edge of 'BALE'.

> To put it simply, if the card responds quickly enough, there is NO
> PROBLEM.

No.  Notice above that MEMCS16 must be valid on the falling edge of
BALE.  But the SA addresses aren't valid until the falling edge of
BALE.

Therefore, "quick enough" could mean zero time, and you can't
guarantee that.

Often, the addresses will be valid before BALE falls.  But sometimes
they might not be (and in fact sometimes aren't in IBM designs), so
you have to live by the rules if you want to be reliable.
-- 
James R. Van Artsdalen          james@bigtex.cactus.org   "Live Free or Die"
Dell Computer Co    9505 Arboretum Blvd Austin TX 78759         512-338-8789