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From: garyt@ios.Convergent.COM (Gary Tse)
Newsgroups: comp.sys.ibm.pc.hardware
Subject: Re: i486 burst mode on Micronics MB?
Message-ID: <1104@ios.Convergent.COM>
Date: 19 Feb 91 00:38:20 GMT
References: <12328.27af2b88@ecs.umass.edu> <3658@bruce.cs.monash.OZ.AU>
Organization: Raoul Duke School of Journalism
Lines: 22

herbie@bruce.cs.monash.OZ.AU (Andrew Herbert) writes:
-  I'm uncertain about whether burst mode is used on Micronics boards, and am
-  not even sure whether it's relevant in a 486 system with a secondary cache -
-  any *informed* comment on this?

Well, it will take hundreds of nanoseconds to fetch a new cache line
from memory.  3 extra clocks from not bursting is no big deal when
you're already willing to pay that kind of penalty for a cache line.  

With a second level cache, it will take (if you're reasonably clever
with your design) no wait states on the critical word.  Then the 3 
non-burst clocks start eating seriously into your cache line fill 
time. 

So in a manner of speaking bursting is not important in a i486 system
without a second level cache.  But you should remember to say this in
the same breath as you say performance really isn't all that important
in an i486 system.

-- 
Gary Tse,  garyt@ios.Convergent.COM  ||  tse@soda.Berkeley.EDU
"Computers are like Old Testament gods; lots of rules and no mercy."