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From: bmarsh@cod.NOSC.MIL (William C. Marsh)
Newsgroups: comp.sys.ibm.pc.hardware
Subject: Re: Dual monitors
Message-ID: <2852@cod.NOSC.MIL>
Date: 20 Feb 91 20:44:30 GMT
References: <169@cf_su20.cf_su10.Sbi.COM> <2819@cod.NOSC.MIL> <5621@bwdls58.UUCP>
Organization: Naval Ocean Systems Center, San Diego
Lines: 39

In article <5621@bwdls58.UUCP> mlord@bwdls58.bnr.ca (Mark Lord) writes:
>In article <2819@cod.NOSC.MIL> bmarsh@cod.nosc.mil.UUCP (William C. Marsh) writes:
><Sorry, the EGA/VGA interface is only 8 bits wide, so even if your VGA
><connects to the '16 bit' connector, the board itself can only do 8 bits
><at a time.  If you look at the memory architecture on the board, you will
><also notice that it is (256, 512, ot 1024) x 8 bits.  All the cards 'fake'
><16 bit accesses in graphics mode.

>Utter rubbish!  The paradise vga card I have has memory that is 16 bits wide,
>and it does indeed use 16-bit writes to update it (in text mode at the least).

That doesn't mean the VGA actually has 16 bit wide data paths to/from display
memory.  Read *any* EGA/VGA reference and you can see that the internal data
path is 8 bits.

><And anyway, all memory accesses to video memory is sync'd to H or V retrace
><time, so 16 vr. 8 bits really don't amount to much.  (Even in the VRAM 
><adapters too!  What a waste!)

>I don't know that much about the VRAM things, but the whole idea of using
>dual-ported VRAMs is to overcome the need to wait for retrace cycles before
>writing, so this statement is probably as accurate as the first paragraph was.

A 10 Mhz, No Wait 286 can move approxamatly 2 Mbyte/sec with memory move
instructions, and yet, the 'fastest' VGA card claims to have about 
11K chars/sec.  These tests do not use the BIOS interface, but go directly to
the memory buffer.  How can you explain two orders of magnitude?

The basic fact is that the video boards on the PC are *not* a true multi-port
ram, just a simple arbitrator, with the retrace getting the highest priority.
(I think I remember reading in my VRAM Tech Ref. that you get one cycle out
of five during active display times).

Bill
-- 
Bill Marsh, Naval Ocean Systems Center, San Diego, CA
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