Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!helios!bcm!dimacs.rutgers.edu!mips!hal!mark
From: mark@mips.COM (Mark G. Johnson)
Newsgroups: comp.arch
Subject: Re: National Semiconductor's Swordfish (commercial)
Message-ID: <46089@mips.mips.COM>
Date: 21 Feb 91 21:47:21 GMT
References: <5403@taux01.nsc.com>
Sender: news@mips.COM
Reply-To: mark@mips.COM (Mark G. Johnson)
Organization: MIPS Computer Systems, Inc.
Lines: 42

In article <5403@taux01.nsc.com> gideon@nsc.nsc.com (Gideon Intrater) writes:
 (press release regarding National Semi Swordfish chip.  Includes:)
>
>
>NATIONAL SEMICONDUCTOR ANNOUNCES 100-MIPS IMAGING TECHNOLOGY
>WITH DIGITAL SIGNAL PROCESSING:  OPENS NEW MARKETS FOR
>PERIPHERALS, ROBOTICS AND MULTIMEDIA
>
>February 15, 1991 -- National Semiconductor Corporation today
>disclosed a new generation of imaging technology that achieves
>an unprecedented 100 MIPS performance by combining a 64-bit
>superscalar architecture with high-performance, on-chip digital
>signal processing.
>
>


Thanks, Gideon.  Readers are certainly very interested in this material.
Here are a couple of more quotes, from the conference paper on 
Swordfish.  Reference: R. Talmudi et al, "A 100MIPS, 64b Superscalar
Microprocessor with DSP Enhancements", paper TAM 5.6, 1991 International
Solid State Circuits Conference, Digest of Technical Papers, pp. 100-101.

line 33|  "Complex number operations, which are common in DSP applications,
       |   are supported by instructions which execute signed 16x16
line 35|   multiplication in one clock cycle and produce a 32b signed result.
       |   Operands for these instructions may be taken either from the
line 37|   16 most significant or from the 16 least significant bits of the
       |   32b integer registers so that real and imaginary parts of a
line 39|   complex number may be stored in a single register and easily
       |   handled."
       |   .....
       |
line 67|  "The 4kB instruction and 1kB data caches are two-way set
       |   associative.  To keep the data cache coherent with the external
line 69|   memory, bus snooping logic tracks the external transactions, and
       |   invalidates the relevant data cache line when data is modified
line 71|   in the external memory."
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086
	(408) 524-8308    mark@mips.com  {or ...!decwrl!mips!mark}


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