Path: utzoo!mnetor!tmsoft!torsqnt!lethe!yunexus!ists!helios.physics.utoronto.ca!news-server.csri.toronto.edu!cs.utexas.edu!uunet!shelby!portia.stanford.edu!elaine26.stanford.edu!dhinds From: dhinds@elaine26.stanford.edu (David Hinds) Newsgroups: comp.arch Subject: Re: 64-bit addressing Message-ID: <1991Feb19.170402.14077@portia.Stanford.EDU> Date: 19 Feb 91 17:04:02 GMT References: <4270@lectroid.sw.stratus.com> <1991Feb18.032849.16544@uicbert.eecs.uic.edu> Sender: news@portia.Stanford.EDU (Mr News) Organization: Stanford University - AIR Lines: 19 In article raje@dolores.Stanford.EDU (Prasad Raje) writes: > >First the statement: > >A 64 bit address will be able to address each byte in a memory array >10.4 kilometers on each side, populated chock full with 1Gbit DRAMs. > How about using holographic memories? I saw a description in BYTE a few months back, that Bellcore has prototypes with storage densities of 10^12 bits per cubic centimeter. By my calculations, a cube 2.6 meters per side would have a capacity of 2^64 bits. Double the edge length to get 2^64 bytes. This is non-volatile storage, and retrieving a page of 100K bits takes "a nanosecond". The I/O interface would have to be able to handle 10^15 bits/second to keep up with this, but then you could read the entire cube in a few hours. I suspect this may take a few years to develop. -David Hinds dhinds@cb-iris.stanford.edu Brought to you by Super Global Mega Corp .com