Xref: utzoo comp.arch:21021 comp.sys.sgi:8446 Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!uunet!jarthur!usc!wuarchive!udel!princeton!phoenix.Princeton.EDU From: dmlaur@phoenix.Princeton.EDU (David M. Laur) Newsgroups: comp.arch,comp.sys.sgi Subject: The Future (64 bits) and SGI quad-word alignment Keywords: alignment SGI 64-bit portable graphics Message-ID: <6518@idunno.Princeton.EDU> Date: 22 Feb 91 20:48:35 GMT Sender: news@idunno.Princeton.EDU Followup-To: comp.sys.sgi Organization: Princeton University, Princeton, New Jersey Lines: 45 --------- long ago, Kurt Akeley of SGI said ---------- >From: kurt@cashew.asd.sgi.com (Kurt Akeley) >Subject: Re: Efficient use of lighting models >Date: 29 Oct 90 20:43:05 GMT > >Here's the facts, make of them what you will. Vertex data are transferred >to GTX and VGX graphics systems using special 3-way operations (see other >SGI publications for explanation). A 3-way transfer takes 10 bus clocks to >complete if its data are quad-word aligned, 14 bus clocks otherwise. Since >the bus clock is always 16 MHz, this translates into 1.6 million aligned >transfers per second, and 1.15 million unaligned transfers per second. >If both transform and fill limits support a call rate that is greater than >1.15 million calls per second (counting each c, n, v, and t call) then >quad-word alignment will improve performance. This situation is common on >well tuned VGX code, somewhat less common on GTX code. So, with respect to allocating "quad-word aligned" space for floating point vertex data AND keeping in mind some of the recently discussed issues in comp.arch viz number of bits in an int/long/float/pointer: Is there a way to (upward) portably allocate space for four-dimensional (e.g. xyzw or xyz,pad) floating point vertices, that will keep performance on the fast path? That is: does "quad-word" also mean "quad-float"? will it continue to mean that if a 64-bit chip comes along? or does "quad-word" mean "4*sizeof(int)" and therefore only happens to affect performance of floats because sizeof(float)==sizeof(int) on the SGI/4D's today. I realize the -lmpc verion of malloc will give a "quad-word" aligned address (whatever that really means). But it's not clear to me if that library should (or can) be used on single-processor systems. More importantly, I'm just trying to understand what aspect of alignment I should really be concerned with when developing data structures. Thanks for any insight; I suppose follow-ups should be to comp.sys.sgi particularly regarding graphics performance issues. ------ David Laur dmlaur@gauguin.princeton.edu Princeton University, Interactive Computer Graphics Lab "Talking about music is like dancing about architecture" - Laurie Anderson Brought to you by Super Global Mega Corp .com