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From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: National Semiconductor's Swordfish microprocessor
Message-ID: <46175@mips.mips.COM>
Date: 25 Feb 91 21:21:13 GMT
References: <49343@apple.Apple.COM> <WOLFE.91Feb20135853@vw.ece.cmu.edu> <1991Feb20.210752.19367@ibmpa.awdpa.ibm.com> <5430@taux01.nsc.com>
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Reply-To: mash@mips.COM (John Mashey)
Organization: MIPS Computer Systems, Inc.
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In article <5430@taux01.nsc.com> gideon@nsc.nsc.com (Gideon Intrater) writes:

>No we don't have an MMU.  Again, we target the processor for imaging embedded 
>applications, where an MMU is usually not required.  Our main design goal
>was to deliver as much performance at a low system cost.  The Swordfish 
>delivers more than 110,000 dhrystones/sec on a 25Mhz bus.

Although I haven't yet seen much detailed data, the swordfish at least
looks like a reasonable implementation consistent with NSC's current
strategy.

However, I would observe that the number of dhrystones related to
bus speed is kind of irrelevant for a processor with on-chip
I-cache and write-back D-cache of any reasonable size....
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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