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From: mac@eleazar.dartmouth.edu (Alex Colvin)
Newsgroups: comp.arch
Subject: Re: Braindamaged architectures (was Re: MIPS, Compaq and Microsoft in bed - NYT story)
Message-ID: <1991Feb26.133509.29017@dartvax.dartmouth.edu>
Date: 26 Feb 91 13:35:09 GMT
References: <45758@mips.mips.COM> <2445@inews.intel.com> <2344@tuvie.UUCP>
Sender: news@dartvax.dartmouth.edu (The News Manager)
Organization: Spurious
Lines: 11

>Just about any architecture which uses 80-bit FP has a way of storing 80
>bits. Otherwise, a context switch has desastrous effects
>(Undeterministic loss of precision between computations. ;-) Actually,
>there once was such a multi-tasking beast (from Honeywell, I think)
>which had 80 bit fp (or whatever) in the FPU, but did not allow saving 
>of the extra precision bits. 

Another Urban legend...
The GE635 (later Honeywell) did use three architectural registers
as an 80 bit FP accumulator, but used 72 bits in floating stores.
However, a context switch stored the registers, all 80 bits worth.


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