Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!zaphod.mps.ohio-state.edu!usc!bbn.com
From: tdonahue@bbn.com (Tim Donahue)
Newsgroups: comp.arch
Subject: Marginal cache (Was: 64bits: Area Overhead and Opportunity Costs)
Message-ID: <62981@bbn.BBN.COM>
Date: 26 Feb 91 20:17:20 GMT
References: <7967@exodus.Eng.Sun.COM> <46046@mips.mips.COM>
Sender: news@bbn.com
Reply-To: tdonahue@bbn.com (Tim Donahue)
Organization: BBN Advanced Computers, Inc.
Lines: 24
In-reply-to: mash@mips.COM (John Mashey)

In article <46046@mips.mips.COM>, mash@mips (John Mashey) writes:
> <stuff about additional area for 64-bit MPU deleted>
>...
>Now, the caches together are about 14% also, so maybe we could have
>doubled one of the caches, which would have been nice.  
>...

OK, John, given the perceived market for the R4000, if you had to choose
which cache to double in size, which would you choose, and why?

>-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>

Cheers,
Tim

Timothy P. Donahue
Operating Systems Development Group
BBN Advanced Computers, Inc.
10 Fawcett Street
Cambridge, MA 02138
(617) 873-6000

tdonahue@bbn.com
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