Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!thunder.mcrcim.mcgill.edu!snorkelwacker.mit.edu!usc!zaphod.mps.ohio-state.edu!pacific.mps.ohio-state.edu!linac!att!pacbell.com!ucsd!hub.ucsb.edu!bears!jackg
From: jackg@bears.uscb.edu (Jack Greenbaum)
Newsgroups: comp.lang.vhdl
Subject: Re: insert design entities in lib STD?
Message-ID: <9423@hub.ucsb.edu>
Date: 25 Feb 91 23:23:30 GMT
References: <3042@laura.UUCP> <1991Feb25.192519.24033@hoss.unl.edu>
Sender: news@hub.ucsb.edu
Reply-To: jackg@bears.ucsb.edu (Jack Greenbaum)
Organization: UCSB ECE
Lines: 18

|> In article <3042@laura.UUCP> dettmer@jupiter.informatik.uni-dortmund.de (Thomas Dettmer) writes:
|> >Hello,
|> >
|> >a question to LRM experts(?):
|> >Packages STANDARD and TEXTIO may not be redefined by the user and reside in
|> >library STD. 
|> >Is it permitted to add other 'local standard' packages in library STD?
|> >
|> >Did I miss something in the LRM?

We use MCC VHDL v3.1. I was able to add the IEEE proposed standard 
multivalue logic package to the library STD, where it happily lives.

-------------------------------------------------------------------------------
Jack Greenbaum      |UC Santa Barbara
jackg@bears.ucsb.edu|Department of Electrical and Computer Engineering, Box 253
(805) 893-4461      |Santa Barbara, Ca. 93106, USA
-------------------------------------------------------------------------------