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From: pefv700@perv.pe.utexas.edu
Newsgroups: comp.unix.shell
Subject: make(1) questions
Message-ID: <44683@ut-emx.uucp>
Date: 25 Feb 91 20:12:04 GMT
Sender: news@ut-emx.uucp
Distribution: usa
Organization: Dept. of Petroleum Engineering, The University of Texas at Aust
Lines: 24


I have 2 executables that are "made" using the same sources files.  The only
difference is that for one a cpp(1) macro is defined, for the other it is not.

It is obvious that if I keep everything in one directory, the best I can do is
to work on one, then make would recompile all of the source files and then the
other could be worked on.  This is acceptable.  However, I cannot think of a
good way to let make know that executable 1 needs the .o files to have been
made with the macro defined while for executable 2 it is just the opposite.

Lastly, my home directory has a $ in it (thanks to an NFS mount to a VAX :-().
I would like to do something like:

PROG=$(HOME)/name

$(PROG): object files...
	cc -o $(PROG) options... object files... libs...

However, the shell (in the cc line) keeps interpreting the $.  Am I out of luck
on this one or can this be fixed?

Thanks,

Chris


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