Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!oakhill!wca
From: wca@oakhill.sps.mot.com (William Anderson)
Newsgroups: comp.arch
Subject: Re: standard extensions
Message-ID: <1991Feb27.220856.4067@oakhill.sps.mot.com>
Date: 27 Feb 91 22:08:56 GMT
References: <1991Feb25.135057.23667@linus.mitre.org> <1991Feb25.201406.18643@bingvaxu.cc.binghamton.edu> <2124@cluster.cs.su.oz.au> <1991Feb27.021435.11296@bingvaxu.cc.binghamton.edu> <1991Feb27.183718.638@jetsun.weitek.COM>
Organization: Motorola Inc., Austin, Texas
Lines: 24

weaver@jetsun.weitek.COM (Mike Weaver) writes:

>Does anyone know of a pipelined divider that gives a result every cycle?

I was under the impression that HP had designed and implemented a multi-
chip FPU with a (partially?) pipelined divider.  It used a model division
(similar to SRT) on every row.  See the proceedings of the 1986 ISSCC (p. 34)
for a description (and die photo) of this divider as well as a clever tree
multiplier.  Judging by this article, HP could cycle the divider only
half as fast (420 nS) as the fully pipelined multiplier (210 nS).  My,
how the clockrates have changed in 5 years....

> ... Also, the actual number of transistors is horrendous -- it would
>take perhaps ten times as many transistors as an array multiplier, which
>is a large thing.

The numbers listed for the (NMOS) parts mentioned above were ~153K
transistors for the multiplier and ~160K for the divider - not an order
of magnitude by any meams.

William Anderson
Motorola 88K Design Group
Motorola MMTG
Austin, TX