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From: rmbult01@ulkyvx.bitnet (Robert M. Bultman)
Newsgroups: comp.arch
Subject: instruction stack
Message-ID: <1991Feb26.112611.808@ulkyvx.bitnet>
Date: 26 Feb 91 11:26:11 GMT
Organization: University of Louisville
Lines: 26

The CDC 6600, 7600, STAR 100, and IBM 360/195 made use of an
instruction stack.  The implementation varied, but generally they were
used to speed up operation of loops.  If a backwards branch referenced
an instruction contained within the instruction stack, the instruction
was obtained from the instruction stack rather than main store.  This
allowed the CPU<->Memory path to be used for data access rather than
instruction fetch.  I have several questions regarding this:

    1) Do any recent (> 1985) machines use this, or has this been
       obviated by the use of cache?

    2) Was this mechanism software controllable, or was it a
       hardware-only mechanism?  (The reference (see below) regarding
       this indicated it was hardware only using an address comparison
       to determine if the backwards jump fell within the limit of the
       instruction stack.  This sounds like a very small i-cache but
       is contained within the CPU.)

    3) Would such a mechanism help RISCs? (Why? Why not?)

Reference:
Topham, Nigel P., Omondi, Amos, and Ibbett, Roland N., "On the Design
and Performance of Conventional Pipelined Architectures", The Journal
of Supercomputing, Vol. 1, No. 4, Aug 1988.

Robert Bultman, University of Louisville, Speed Scientific School