Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!lll-winken!elroy.jpl.nasa.gov!sdd.hp.com!hplabs!hpda!hpcuha!hpcuhd!edwardm
From: edwardm@hpcuhd.HP.COM (Edward McClanahan)
Newsgroups: comp.arch
Subject: Re: 68040 and caches
Message-ID: <105940002@hpcuhd.HP.COM>
Date: 1 Mar 91 19:18:33 GMT
References: <1991Feb27.082251.23059@Neon.Stanford.EDU>
Organization: Hewlett Packard, Cupertino
Lines: 23

> >	Random question concerning the 68040: what do people think about
> >the utility/cost effectiveness/need for external caches (given that it
> >has ?4-way? associative 4K I and D caches internally and a single
> >external bus.  

>   My opinion...  For a Unix type workload, 64K-256K of cache is about
> where you should be now.  For a PC type workload, 32K-64K.  Apple seems
> to have done studies on its IIfx and IIci cache designs which indicate
> that anything more than 32K of cache for the Mac design is overkill.

Another issue to consider is cache coherency in systems with multiple CPUs
or DMA (e.g. most of the machines mentioned).  I do not know what the '040
internal caches do to solve this problem, but external caches which don't
address it (cache coherency) can actually be quite a hassle to program
around.

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

  Edward McClanahan
  Hewlett Packard Company     -or-     edwardm@cup.hp.com
  Mail Stop 42UN
  11000 Wolfe Road                     Phone: (480)447-5651
  Cupertino, CA  95014                 Fax:   (408)447-5039