Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!comp.vuw.ac.nz!windy!srwmcln
From: srwmcln@windy.dsir.govt.nz
Newsgroups: comp.sys.amiga.hardware
Subject: Re: Bridgeboard questions...
Message-ID: <18841.27cba1dd@windy.dsir.govt.nz>
Date: 27 Feb 91 12:11:07 GMT
References: <1991Feb14.034710.11646@mintaka.lcs.mit.edu> <18991@cbmvax.commodore.com> <1991Feb16.044402.12664@mintaka.lcs.mit.edu> <19082@cbmvax.commodore.com>
Organization: DSIR, Wellington, New Zealand
Lines: 13

In article <19082@cbmvax.commodore.com>, daveh@cbmvax.commodore.com (Dave Haynie) writes:
>....
> the future.  Most accelerator cards don't generate a proper bus lock for TAS.
> Most 68020/68030 cards will generate two separate unlocked cycles.  The A3000
> will generate a real TAS read-modify-write cycle, but it may vary by a clock
> or so from what the 68000 does, based on synchronizations between the 68030
> and 7MHz clock.  I don't what a fast 68000 would do.  
>....
Dave, can you give any hints on how to emulate TAS cycles with a 68020 or
68030 (running faster than 7MHz). My casual thoughts on this matter lead me
nowhere!.

Clive.