Path: utzoo!news-server.csri.toronto.edu!cs.utexas.edu!hellgate.utah.edu!caen!sdd.hp.com!spool.mu.edu!uunet!cbmvax!daveh
From: daveh@cbmvax.commodore.com (Dave Haynie)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: Bridgeboard questions...
Message-ID: <19526@cbmvax.commodore.com>
Date: 5 Mar 91 16:36:11 GMT
References: <1991Feb14.034710.11646@mintaka.lcs.mit.edu> <18991@cbmvax.commodore.com> <1991Feb16.044402.12664@mintaka.lcs.mit.edu> <19082@cbmvax.commodore.com> <18841.27cba1dd@windy.dsir.govt.nz>
Reply-To: daveh@cbmvax.commodore.com (Dave Haynie)
Organization: Commodore, West Chester, PA
Lines: 47

In article <18841.27cba1dd@windy.dsir.govt.nz> srwmcln@windy.dsir.govt.nz writes:
>In article <19082@cbmvax.commodore.com>, daveh@cbmvax.commodore.com (Dave Haynie) writes:

>> the future.  Most accelerator cards don't generate a proper bus lock for TAS.
>> Most 68020/68030 cards will generate two separate unlocked cycles.  

>Dave, can you give any hints on how to emulate TAS cycles with a 68020 or
>68030 (running faster than 7MHz). My casual thoughts on this matter lead me
>nowhere!.

There is a software technique, called a "spin-lock", which allows arbitration
between two shared memory coprocessors.  I don't have a reference for this 
offhand.  I think it involves having each processor try to give the semaphore
to the other, rather than the normal approach where each one tries to get the
semaphore for itself.

In hardware, it's pretty easy.   Assuming you have some fast 68020/30 system
which needs a 68000 style TAS cycle, such as the A3000 when talking to the
Zorro II bus.  Any such system already has a state machine of some kind which
will convert 68030 signals into 68000 compatible signals.  The addition to
this will basically have a internally visible iAS* which breaks the lock at all
times.  The externally visible eAS*, the one out on the bus, is conditioned by
the 68030's RMC* strobe.  At the apparent end of the cycle, when the 68030 AS*
is negated, I let the iAS* negate as well.  eAS*, however, is held asserted 
by either iAS* or by RMC*.  All of the other elements of the TAS cycle are very
similar to the normal 68000 cycle, and naturally fall out of your state machine
for basic 68000 cycles.  

The one slight problem with this is in the case of asynchronous processors, 
where the 68030 clock isn't related to the Zorro II bus clock.  In this case,
every 68030 cycle will have a synch-up delay, where the 68030's AS* must wait
for an appropriate point in the 68000 cycle, generally the rising edge of the
7MHz clock, before starting an 68000 compatible cycle.  Since both halves of
the TAS cycle are separate 68030 cycles, there's in general no way to guarantee
that the 68000 style TAS cycle that's generated is always exactly the same
number of clocks as the standard 7MHz 68000 cycle.  This should not be a 
problem, since the 68000/Zorro II bus really doesn't define a synchronous 
cycle, but anything that is depending on the pure synchronous behavior of a
68000 TAS cycle could get into trouble here.

>Clive.


-- 
Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests"
   {uunet|pyramid|rutgers}!cbmvax!daveh      PLINK: hazy     BIX: hazy
	"What works for me might work for you"	-Jimmy Buffett