Path: utzoo!news-server.csri.toronto.edu!cs.utexas.edu!uunet!stanford.edu!msi.umn.edu!src.honeywell.com!milo!shankar
From: shankar@SRC.Honeywell.COM (Subash Shankar)
Newsgroups: comp.sys.apple2
Subject: Re: Zip GSX
Message-ID: <1991Mar5.190734.2818@src.honeywell.com>
Date: 5 Mar 91 19:07:34 GMT
References: <554@generic.UUCP>
Sender: news@src.honeywell.com (News interface)
Organization: Honeywell Systems & Research Center
Lines: 16
Nntp-Posting-Host: milo.src.honeywell.com

In article <554@generic.UUCP> ericmcg@pnet91.cts.com (Eric Mcgillicuddy) writes:

>BTW the hit ratio seems to be in the neighbouhood of 60% with a 16k cache,
>increasing the cache is about the cheapest way to improve performance. I
>expect that a 64k cache will produce close to 90% hit ratio. Although I would
>prefer 256k myself.

Though the 90% figure sounds optimistic to me, I would think it would depend a
lot on what is cached (data or instructions?) and the mapping strategy?  Does
anybody know what kind of cache the Zip chip and the TWGS use?


---
Subash Shankar             Honeywell Systems & Research Center MN65-2100
voice: (612) 782 7558      US Snail: 3660 Technology Dr., Minneapolis, MN 55418
shankar@src.honeywell.com  srcsip!shankar