Path: utzoo!censor!geac!torsqnt!hybrid!scifi!bywater!uunet!dev8h.mdcbbs.com!campbell From: campbell@dev8h.mdcbbs.com (Tim Campbell) Newsgroups: comp.sys.ibm.pc.hardware Subject: Re: Parity chip on Intel Computers Message-ID: <1991Mar1.100548.1@dev8h.mdcbbs.com> Date: 1 Mar 91 10:05:48 GMT References: <1991Feb27.140227.9246@panix.uucp> <1991Feb27.173721.3963@cs.mcgill.ca> Organization: McDonnell Douglas M&E, Cypress CA Lines: 61 Nntp-Posting-Host: dev8h Nntp-Posting-User: campbell In article <1991Feb27.173721.3963@cs.mcgill.ca>, storm@cs.mcgill.ca (Marc WANDSCHNEIDER) writes: > > What is the ninth chip on a Standard PC SIMM for (ie, the so call > 'parity' chip) ...? Why is it that the Intel computers require these and the > AMIGAs and other 680x0 computer do not...? > > ./*- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > storm@cs.mcgill.ca McGill University It's 11pm, do YOU > Marc Wandschneider Montreal, CANADA know what time it is? > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > storm@cs.mcgill.ca McGill University It's 11pm, do YOU > Marc Wandschneider Montreal, CANADA know what time it is? > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- The chips are laid out as follows: +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ 1 2 3 4 5 6 7 8 P (9) Each chip stores 1 bit of the byte. The parity chip simply stores the parity bit (much the same way a parity bit is used in async communications). The Intel computers don't *need* the parity chip (the IBM PCjr is an example of a machine that did not have one), but it's a good idea for any computer. If there is a memory error in one of the chips, the parity chip will catch it and signal an interrupt - this produces an error code on the screen and halts the computer - the code can be used to determine what error has occured - I beleive it also indicates which bank of memory is at fault. The parity scenario works better in memory than it does in communications. A garbled line could in effect mess up an even number of bits which balance each other out - (so the parity still works out) - there's about a 50% chance that the parity will work. In the memory, the only way to fool the parity checking is for 2 chips (or any even number) to fail and flip their bits at EXACTLY the same time. This is not likely to happen naturally. Other computers are not immune to parity errors. Although they are rare, the PC's would detect them. Other machines (you indicated the Amiga as an example) would simply be oblivious to the fact that memory has failed. IBM machines also do memory checks at power up. I'm not sure the Amiga does this. If it does not, a user could potentially have to learn about his failed memory chip the hard way. -Tim --------------------------------------------------------------------------- In real life: Tim Campbell - Electronic Data Systems Corp. Usenet: campbell@dev8.mdcbbs.com @ McDonnell Douglas M&E - Cypress, CA also: tcampbel@einstein.eds.com @ EDS - Troy, MI CompuServe: 71631,654 Prodigy: MPTX77A P.S. If anyone asks, just remember, you never saw any of this -- in fact, I wasn't even here.