Path: utzoo!news-server.csri.toronto.edu!rutgers!usc!wuarchive!udel!nigel.ee.udel.edu!mccalpin From: mccalpin@perelandra.cms.udel.edu (John D. McCalpin) Newsgroups: comp.sys.sgi Subject: 4D/3x0 memory bandwidth Message-ID: Date: 6 Mar 91 13:35:49 GMT Sender: usenet@ee.udel.edu Distribution: usa Organization: College of Marine Studies, U. Del. Lines: 15 Nntp-Posting-Host: perelandra.cms.udel.edu I am working on some performance modelling for shared-memory multiprocessor machines and I was wondering if anyone out there could tell me the memory bandwidth on the SGI 4D/3x0 series machines. I am most interested in the main memory to secondary cache link, but the secondary cache to primary cache link is of interest also. I believe that the cpu's all share the same secondary cache, so that I would assume that the main memory is single-ported. Is the secondary cache multi-ported, or do the cpu's access it via a shared bus? Thanks for any answers! -- John D. McCalpin mccalpin@perelandra.cms.udel.edu Assistant Professor mccalpin@brahms.udel.edu College of Marine Studies, U. Del. J.MCCALPIN/OMNET