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From: rpw3@rigden.wpd.sgi.com (Rob Warnock)
Newsgroups: comp.arch
Subject: Re: register save
Message-ID: <90092@sgi.sgi.com>
Date: 10 Mar 91 12:37:26 GMT
References: <3219@crdos1.crd.ge.COM> <1991Mar7.063957.17197@quick.com>
Sender: guest@sgi.sgi.com
Reply-To: rpw3@sgi.com (Rob Warnock)
Organization: Silicon Graphics, Inc., Mountain View, CA
Lines: 17

In article <1991Mar7.063957.17197@quick.com> srg@quick.com
(Spencer Garrett) writes:
+---------------
| You could get a lot more performance from this technique if you
| could introduce some hysteresis into the process (ie - don't restore
| a register until you get back to a routine that uses it), but
| this would be a nightmare to implement, since registers would have
| to be saved and restored from different stack frames.
+---------------

This is *exactly* what the Am29000 stack-cache register windowing does
for you -- provides a *large* amount of hysteresis in the "spill/fill"
activity, so much so that register spill/fills generally account for well
under 1% of all cycles (Dhrystone/grep/diff/nroff/asm/Stanford, etc.).


-Rob