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From: torek@elf.ee.lbl.gov (Chris Torek)
Newsgroups: comp.arch
Subject: Re: VM Measurement
Message-ID: <10805@dog.ee.lbl.gov>
Date: 11 Mar 91 09:55:44 GMT
References: <12318@pt.cs.cmu.edu>
Reply-To: torek@elf.ee.lbl.gov (Chris Torek)
Organization: Lawrence Berkeley Laboratory, Berkeley
Lines: 35
X-Local-Date: Mon, 11 Mar 91 01:55:44 PST

In article <12318@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu
(Donald Lindsay) writes:
>The MIPS chips have a unique advantage here. MIP's TLB refill is done
>by software, hence, a user could in theory boot an instrumented
>version of the OS.  I suggest collecting, per page, a count of how
>many times that page is faulted in to the TLB.

The Sun MMUs in the Sun-3 and Sun-4 series (the Sun-2 as well, but the
Sun-2 is essentially dead) have a somewhat similar property.  The MMU
itself is a piece of SRAM with some hardware logic around it; the SRAM
is too small to map even a single process, so you must `demand load' it
at fault time:

	fault_handler:
		va = instruction_access_fault ? pc : saved_va;
		if (mmu entry for va is out of date) {
			reload mmu entry;
			retry;
		}
		if (pagein(va) succeeds) {
			reload mmu entry;	/* if not part of pagein */
			retry;
		}
		deliver fault to process;

The `MMU entry's are actually collections of 16 (Sun-3), 32 (Sun-4), or
64 (Sun-4c) PTEs (individual PTEs are addressed much like words in
cache lines).  You can even do counting without taking faults on each
PTE (take only one fault per `PTE line').  There are reference bits in
each PTE.  If you turn them off whenever you load a new PTE line, then
when you swap out an old line and collect its reference bits, the va's
corresponding to any one PTE were used iff the ref bit is on.
-- 
In-Real-Life: Chris Torek, Lawrence Berkeley Lab EE div (+1 415 486 5427)
Berkeley, CA		Domain:	torek@ee.lbl.gov