Path: utzoo!news-server.csri.toronto.edu!rutgers!mit-eddie!uw-beaver!tera.com!bob
From: bob@tera.com (Bob Alverson)
Newsgroups: comp.arch
Subject: Re: Divide in 1 cycle
Message-ID: <1991Mar12.043839.11068@tera.com>
Date: 12 Mar 91 04:38:39 GMT
References: <1991Mar7.043931.13552@bingvaxu.cc.binghamton.edu> <777@spim.mips.COM> <1991Mar8.110801.20042@bingvaxu.cc.binghamton.edu>
Sender: news@tera.com (News Administrator)
Organization: Tera Computer Company, Seattle, WA
Lines: 14

Although the Tera computer is not built yet, it will be able to divide by
an arbitrary integer *constant* (or loop invariant value, etc.), while
producing one result per cycle.  Mind you, I can't imagine any reason
anyone would care.  The latency is the same as for a "fused multiply add"
a la IBM's RS/6000 (because the divide is done with the same logic).

For the unlucky whose divisors aren't known to the compiler and aren't loop
invariant, the divide rate drops to one result every nine ticks.  The only
significant hardware dedicated to divide is a 256 entry lookup table and
an 8x8 -> 16 multiplier for the initial reciprocal approximation.

Now, if I could just figure out how to do float divides at one per tick...

Bob (bob@tera.com)