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From: lindsay@gandalf.cs.cmu.edu (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: 68040 and caches
Message-ID: <12143@pt.cs.cmu.edu>
Date: 28 Feb 91 05:03:12 GMT
References: <19330@cbmvax.commodore.com>
Organization: Carnegie Mellon RI/ School of CS
Lines: 37


In article <19330@cbmvax.commodore.com>
	jesup@cbmvax.commodore.com (Randell Jesup) writes:
>	Random question concerning the 68040: what do people think about
>the utility/cost effectiveness/need for external caches (given that it
>has ?4-way? associative 4K I and D caches internally and a single
>external bus.

Claimed results from HP (for the HP 425t and HP 425s, both 25 MHz) are:

KB of external cache:	0	128

overall SPECmark	11	11.8
Integer SPECs		12.3	12.9
Float   SPECs		10.2	11

Note that this is at 25 MHz. What this data is saying, is that the
disparity between onchip cache, and main memory, is not extreme
enough.  [For this benchmark suite] few systems can justify adding an
intermediate level to the memory heirarchy.

A higher clock rate, or a slower main memory, would cause a bigger
disparity. Eventually, the external cache would be reasonable, to
reduce the penalty of the onchip cache misses.

Note, by the way, that second-level caches have to be much larger
than first-level caches. This is because the first-level cache skims
the cream, and any second-level cache sees an address stream with
most of its locality removed. With bad locality, a small cache isn't
going to help. Luckily, the second-level cache only has to be prompt,
not screamingly fast, so it isn't *that* expensive to build one.




-- 
Don		D.C.Lindsay .. temporarily at Carnegie Mellon Robotics