Xref: utzoo comp.arch:21452 comp.protocols.nfs:1971 Newsgroups: comp.arch,comp.protocols.nfs Path: utzoo!henry From: henry@zoo.toronto.edu (Henry Spencer) Subject: Re: Incremental sync()s and using disk idle time Message-ID: <1991Mar15.165124.18039@zoo.toronto.edu> Date: Fri, 15 Mar 1991 16:51:24 GMT References: <28975@cs.yale.edu> <1991Mar12.202238.19586@zoo.toronto.edu> <3254@crdos1.crd.ge.COM> <3265@crdos1.crd.ge.COM> Organization: U of Toronto Zoology In article <3265@crdos1.crd.ge.COM> davidsen@crdos1.crd.ge.com (bill davidsen) writes: >Every interrupt will require a context switch in and out of the >interrupt handler. The only real low cost way to do this is to have a >set of dedicated interrupt registers (like the 2nd register set of the >Z80), and I bet no one will suggest that a CPU should dedicate area to a >set of registers just to avoid a smart controller. Nonsense. If the handling of the interrupt is sufficiently trivial, several modern CPUs -- e.g. the 29k -- can do it without a full context switch, by having a small number of registers dedicated to it. This is a very cost-effective use of silicon, adding a small amount to the CPU to avoid the hassle and complexity of smart controllers. Efficient fielding of simple interrupts (ones that require no decision making) is, in any case, a solved problem even for older CPUs. It just takes some work and some thought. Blindly taking a context switch for such trivial servicing is a design mistake. -- "But this *is* the simplified version | Henry Spencer @ U of Toronto Zoology for the general public." -S. Harris | henry@zoo.toronto.edu utzoo!henry