Path: utzoo!attcan!uunet!math.fu-berlin.de!opal!unido!uklirb!kirchner
From: kirchner@informatik.uni-kl.de (Reinhard Kirchner)
Newsgroups: comp.arch
Subject: Re: instruction stack
Message-ID: <7593@uklirb.informatik.uni-kl.de>
Date: 1 Mar 91 11:37:17 GMT
References: <1991Feb26.112611.808@ulkyvx.bitnet>
Sender: news@uklirb.informatik.uni-kl.de
Lines: 24

From article <1991Feb26.112611.808@ulkyvx.bitnet>, by rmbult01@ulkyvx.bitnet (Robert M. Bultman):
> 
>     1) Do any recent (> 1985) machines use this, or has this been
>        obviated by the use of cache?
> 
>     2) Was this mechanism software controllable, or was it a
>        hardware-only mechanism?  (The reference (see below) regarding
>        this indicated it was hardware only using an address comparison
> 
>     3) Would such a mechanism help RISCs? (Why? Why not?)
> 
The already mentioned Hyperstone does something like this, even if it is
called 'cache' . The load a circular buffer with the executed instructions
and have them at hand in a loop. They do an automated prefetch and have also
an instruction to start a certain amount of prefetching ( max. 8 words ).
This seems to be implementable with very little amount of transistors
and seems to generate a lot of speed ( the Hyperstone has only 85k Transistors)
Since the processor has special means for sequential access in the same
RAM page prefetching allows using this and avoids intermixed instruction
and data fetches.

Reinhard Kirchner
Univ. Kaiserslautern, Germany
kirchner@uklirb.informatik.uni-kl.de