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From: mslater@cup.portal.com (Michael Z Slater)
Newsgroups: comp.arch
Subject: Re: Data General NEW AVIION machine
Message-ID: <40198@cup.portal.com>
Date: 15 Mar 91 23:42:51 GMT
References: <1991Mar14.134319.22796@news.larc.nasa.gov>,
 <1991Mar14.184416.3251@berlioz.nsc.com>
  <00945A37.DC86CCE0@KING.ENG.UMD.EDU>
Organization: The Portal System (TM)
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>I read from the newspaper that good old Data General is introduced
>a new AViiON machine that is 115 MIPS.  And the machine is available
>today (better than MIPS and Moto to introduce only their plans).

MIPS ratings of multiprocessor machines aren't necessarily meaningful.
If I have one task I want to run, that 115 MIPS machine is only one-fourth
that speed. (It is a four-processor system.)

The most interesting part of it, from my point of view, is that is uses
a new cache/MMU chip that Moto announced at the same time. The 88204 CMMU
has 64 Kbytes of cache RAM on a single chip, along with the cache control
and MMU. That's right, 64K with no external SRAMs. It's priced at $495 in
1000s and avilability is promised for April.

The press release doesn't say whether any improvements were made to the CMMU
other than quadrupling its size. The size alone is impressive, and is 
especially useful in an MP system where minimizing memory bus bandwidth used
by each processor it critical.

Michael Slater, Microprocessor Report  mslater@cup.portal.com