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From: my@tern.nsc.com (Michael Yip)
Newsgroups: comp.arch
Subject: Re: Data General NEW AVIION machine
Keywords: Data General, Avvion, 88000, 88K, MIPS, Motorola, UNIX
Message-ID: <1991Mar16.073539.823@berlioz.nsc.com>
Date: 16 Mar 91 07:35:39 GMT
References: <40198@cup.portal.com> <1991Mar14.134319.22796@news.larc.nasa.gov>,
Sender: news@berlioz.nsc.com
Reply-To: my@tern.nsc.com (Michael Yip)
Organization: National Semiconductor Corporation
Lines: 39


> MIPS ratings of multiprocessor machines aren't necessarily meaningful.
> If I have one task I want to run, that 115 MIPS machine is only one-fourth
> that speed. (It is a four-processor system.)
I agree with you.  But I think that DG's target is multiuser system which 
support many users at the same time.  That is quite a bit of difference
from a super-desktop-personal-workstation which will probably benefit more 
from a high MIPS single processor system.

How fast is each processor anyway?  Let's see ... 115/4 = 31 MIPS ...
so the processor is 40MHz?  (Is 88K a super-scaler?  Not yet, right?)


> The most interesting part of it, from my point of view, is that is uses
> a new cache/MMU chip that Moto announced at the same time. The 88204 CMMU
> has 64 Kbytes of cache RAM on a single chip, along with the cache control
> and MMU. That's right, 64K with no external SRAMs. It's priced at $495 in
> 1000s and avilability is promised for April.
Nice.  By the way, do you know if Moto implemented the 88204 CMMU with
2T or 4T cells?  Also, if the 88204 is a first level cache, is DG 
implementing a second level cache?  (Or it's getting too complicated to 
do that on a multiprocessor system?)  

It will be nice if the 88204 CMMU offers onchip first level cache and
support external SRAM from second level cache using the just one chip.;)


> The press release doesn't say whether any improvements were made to the CMMU
> other than quadrupling its size. The size alone is impressive, and is 
> especially useful in an MP system where minimizing memory bus bandwidth used
> by each processor it critical.
By the way, what cahce protocol does the 88204 use to support multiprocessor
system?  (See i don't know much about the 88K family.)

-- Mike Yip
   my@berlioz.nsc.com