Path: utzoo!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!unix.cis.pitt.edu!pitt!vax.cs.pitt.edu!jonathan From: jonathan@cs.pitt.edu (Jonathan Eunice) Newsgroups: comp.arch Subject: cache pre-load/no-load instructions Message-ID: Date: 17 Mar 91 08:44:38 GMT Sender: news@pitt.UUCP Organization: University of Pittsburgh Computer Science Lines: 19 Two of the tweaks of the forthcoming "Snake" (HP-PA 1.1) systems from HP are: 1) cache pre-load instructions (the compiler inserts these into the instr stream, and hopefully, the appropriate cache line will be available by the time it's needed, avoiding delays and speeding up single-task execution) 2) cache no-load hints as a part of store instructions (useful to avoid useless cache loading for initialization statements, for faster program startup, and perhaps in other situations too) How effective are these optimizations likely to be? (While they aren't going to give the same kind of speedup as making the system super-scalar or super-pipelined, they strike me as effective tweaks.) Does anyone else have them? I seem to recall a posting to the effect that the RS/6000 POWER architecture does not. What about MIPS, SPARC, etc? Is this a me-too feature?