Path: utzoo!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!decwrl!world!iecc!compilers-sender From: preston@ariel.rice.edu (Preston Briggs) Newsgroups: comp.compilers Subject: Re: C Compilers which use full 486 capabilities Keywords: 486, optimize Message-ID: <1991Mar15.173551.13702@rice.edu> Date: 15 Mar 91 17:35:51 GMT References: <9103130754.AA19293@gara.une.oz.au> Sender: compilers-sender@iecc.cambridge.ma.us Reply-To: preston@ariel.rice.edu (Preston Briggs) Organization: Rice University, Houston Lines: 20 Approved: compilers@iecc.cambridge.ma.us mason+@transarc.com (Tony Mason) writes: >[quoting from Dr. Dobbs] >"The 486 represents a fundamental break with 8088-style optimization. >Virtually all the old rules fail on the 486, where, incredibly, a move >to or from memory often takes just one cycle, but exchanging two >registers takes three cycles." Does anyone's compiler generate an exchange instruction? I can visualize uses, but I'm not sure how I'd recognize it. I can imagine peephole optimizers that could catch it, but generally, I dislike instructions with more than 1 result. How would it integrate with register allocation? Preston Briggs [As far as I can tell, most actual XCHG instructions are really test-and-sets that set locks between processes or processors. -John] -- Send compilers articles to compilers@iecc.cambridge.ma.us or {ima | spdcc | world}!iecc!compilers. Meta-mail to compilers-request.